)]}'
{
  "commit": "6d7eabe699b3fab187db2ceff76fcbb24cd798e7",
  "tree": "4bd952c79253a995db379bdeb8d12fc5bdfe798e",
  "parents": [
    "e0a236ac1fd1f797c7796eaa48fd29220d947c03",
    "195568163cd1ec7bf9cf3ef394fbefb73ce94768"
  ],
  "author": {
    "name": "Seth Hoenig",
    "email": "shoenig@duck.com",
    "time": "Thu Mar 23 07:52:12 2023 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Mar 23 07:52:12 2023 -0500"
  },
  "message": "Merge pull request #1 from shoenig/cache-info\n\nm1cpu: fetch l1, l2 cache data for p/e cores",
  "tree_diff": []
}