)]}'
{
  "commit": "195568163cd1ec7bf9cf3ef394fbefb73ce94768",
  "tree": "4bd952c79253a995db379bdeb8d12fc5bdfe798e",
  "parents": [
    "e0a236ac1fd1f797c7796eaa48fd29220d947c03"
  ],
  "author": {
    "name": "Seth Hoenig",
    "email": "shoenig@duck.com",
    "time": "Thu Mar 23 07:50:20 2023 -0500"
  },
  "committer": {
    "name": "Seth Hoenig",
    "email": "shoenig@duck.com",
    "time": "Thu Mar 23 07:50:20 2023 -0500"
  },
  "message": "m1cpu: fetch l1, l2 cache data for p/e cores\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e04c9ee11f7fd21e0e5ca55a63398ead187d6bc1",
      "old_mode": 33188,
      "old_path": "cpu.go",
      "new_id": "5a5d9b332a14d7f7f7a87eeac9b5ed4fb47825fb",
      "new_mode": 33188,
      "new_path": "cpu.go"
    },
    {
      "type": "modify",
      "old_id": "34f32e1ebfa225117cfc4ebd5b289ffba4338f35",
      "old_mode": 33188,
      "old_path": "cpu_test.go",
      "new_id": "704d13a71f78e94bc9633b2bb44dfd9ce5ceb169",
      "new_mode": 33188,
      "new_path": "cpu_test.go"
    }
  ]
}